1. Field of the Invention
The present invention relates to a voltage controlled oscillator, and more specifically to a voltage controlled oscillator having an oscillation frequency variation minimized in comparison with a power supply voltage variation.
2. Description of Related Art
For example, Ian A. Young et al., xe2x80x9cA PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessorsxe2x80x9d, IEEE Journal of Solid State Circuits, Vol. 27, No. 11, pp.1599-1607, November 1992, proposes one prior art voltage controlled oscillator, the disclosure of which is incorporated by reference in its entirety into this application.
Referring to FIG. 1, there is shown a circuit diagram of one example of the prior art voltage controlled oscillator based on the above quoted paper. This prior art voltage controlled oscillator includes a ring oscillator constituted of a plurality of differential amplifier type delay circuits 912 which are connected in cascade to form a closed ring by feeding back an output of a last stage delay circuit to an input of a first stage delay circuit, a dummy bias circuit 911 and a voltage-to-current converter 910, coupled as shown.
Each of the delay circuits 912 includes a pair of pMOS transistors MP101 and MP102 having their sources common-connected to each other o form a differential pair, a constant current source pMOS transistor MP103 connected between a first power supply voltage terminal 920 and the common-connected sources of the pMOS transistors MP101 and MP102, and a pair of voltage controlled resistors 901 connected, as a load, between a drain of the pMOS transistors MP101 and MP102 and a second power supply voltage terminal 921, respectively. Here, the voltage controlled resistor means a resistor having its resistance value which can be controlled by the magnitude of an applied voltage. A low level of an output of each delay circuit 912 (namely, an output of the oscillator) is at a potential level of the second power supply voltage terminal 921. Assuming that a current value of the associated constant current source MP103 is xe2x80x9cIxe2x80x9d and a resistance value of the associated voltage controlled resistors 901 is xe2x80x9cRxe2x80x9d, a high level of the output of each delay circuit 912 is a potential level which is higher than the potential level of the second power supply voltage terminal 921, by a voltage of xe2x80x9cRxc2x7Ixe2x80x9d.
Furthermore, an input-to-output delay time of each delay circuit 912 is determined by both of a potential difference between a potential level of a current control signal line 930 and a potential level of the first power supply voltage terminal 920, and a potential difference between a potential level of a voltage control signal line 931 and a potential level of the second power supply voltage terminal 921. Namely, the input-to-output delay time is determined by a gate-source voltage of the constant current source pMOS transistor MP103 (constant current value) and the resistance value of the voltage controlled resistors 901 functioning as a load resistor.
In addition, an oscillation frequency of the signal obtained from an output terminal 922 is determined by a potential difference between a potential level on a control terminal 923 of the voltage-to-current converter 910 and the potential level of the second power supply voltage 921, by action of the voltage-to-current converter 910.
The dummy bias circuit 911 operates to determine a potential level of the voltage control signal line 931 to the effect that the signal obtained from an output terminal 922 assumes a high level equal to a potential level given to an amplitude control terminal 924 and a low level equal to the potential level of the second power supply voltage 921.
In brief, the dummy bias circuit 911 comprises, similarly to the delay circuit 912, a constant current source pMOS transistor MP103, a differential transistor pair consisting of a pair of pMOS transistors MP101 and MP102, and a pair of voltage controlled resistors 901 functioning as a load resistor. The dummy bias circuit 911 further includes an operational amplifier OP1 having an inverting input connected to the amplitude control terminal 924 and a non-inverting input connected to a connection node N1 between one transistor MP102 of the differential transistor pair and the associated voltage controlled resistor 901. An output of the operational amplifier OP1 is applied to a control input of the voltage controlled resistors 901 in the dummy bias circuit 911, thereby to make a potential of the node N1 equal to a high level reference voltage applied to the amplitude control terminal 924. Furthermore, the output of the operational amplifier OP1 is applied through the current control signal line 931 to a control input of all the voltage controlled resistors 901 of the delay circuits 901, so that the high level of the signal obtained from an output terminal 922 becomes equal to the high level reference voltage given to an amplitude control terminal 924.
With the above mentioned arrangement, even if the current value of the constant current source in each delay circuit 912 is caused to change (namely, the oscillation frequency is changed), the amplitude of the signal obtained from an output terminal 922 is maintained at a constant magnitude.
In the above mentioned prior art voltage controlled oscillator, in ordinary cases, the potential level of the signal supplied to the control terminal 923 varies or fluctuates in phase with the voltage level of the second power supply voltage terminal 921. Therefore, even if the voltage level of the second power supply voltage terminal 921 varies or fluctuates, the oscillation frequency of the signal obtained from the output terminal 922 is subjected to almost no influence.
However, when the voltage level of the first power supply voltage terminal 920 varies or fluctuates, the voltage-to-current converter 910 controls the potential level of the current control signal line 930 in order to avoid variation of the input-to-output delay time of each delay circuit 912. However, if the frequency of the variation or fluctuation of the voltage level of the first power supply voltage terminal 920 becomes as high as the voltage-to-current converter 910 cannot follow the voltage level variation or fluctuation, the input-to-output delay time of each delay circuit 912 changes, with the result that the oscillation frequency of the signal obtained from the output terminal 922 changes. As a result, for example, it is not possible to cope with a temporary voltage drop within a LSI (large scaled integrated circuit) chip caused because a current starts or stops flowing when a part of circuits in the LSI chip starts or stop operating.
Here, the frequency of the voltage level variation or fluctuation which the voltage-to-current converter 910 cannot follow, is determined by a parasitic capacitance of the current control signal line 930, a gate capacitance of the pMOS transistors having a gate connected to the current control signal line 930, and the characteristics of a pMOS transistor which constitutes the current control signal line 930.
Accordingly, it is an object of the present invention to provide a voltage controlled oscillator which has overcome the above mentioned defect of the conventional one.
Another object of the present invention is to provide a voltage controlled oscillator having an oscillation frequency variation minimized in comparison with a power supply voltage variation.
The above and other objects of the present invention are achieved in accordance with the present invention by a voltage controlled oscillator including:
an oscillator connected between a high potential power supply line and a low potential power supply line, for generating an oscillation signal having a frequency changing dependently upon a voltage difference between the high potential power supply line and the low potential power supply line, and
a transistor connected between one of the high potential power supply line and the low potential power supply line and a power supply terminal for supplying a voltage to the one of the high potential power supply line and the low potential power supply line,
a control signal being applied to a control electrode of the transistor to control the frequency of the oscillation of the oscillator.
In one variation, the transistor is a MOS transistor having a source connected to the one of the high potential power supply line and the low potential power supply line, and a drain connected to the power supply terminal, the control signal being applied to a gate electrode of the MOS transistor.
In another variation, the transistor is a bipolar transistor having an emitter connected to the one of the high potential power supply line and the low potential power supply line, and a collector connected to the power supply terminal, the control signal being applied to a base electrode of the MOS transistor.
In a preferred embodiment, the voltage controlled oscillator further includes a level shift means connected to the high potential power supply line, the low potential power supply line and the power supply terminal, the level shift means receiving the oscillation signal of the oscillator and converting a level of the oscillation signal corresponding to a potential of the one of the high potential power supply line and the low potential power supply line, to a voltage level of the power supply terminal.
More preferably, the oscillator has a control terminal in addition for a terminal for the high potential power supply line, a terminal for the low potential power supply line, and a terminal for the output signal, and the oscillator is configured to be capable of controlling the frequency of the oscillation signal of the oscillator by means of a voltage applied to the control terminal.
According to another aspect of the present invention, there is provided a voltage controlled oscillator comprising:
an oscillator connected between a first power supply line and a second power supply line and having an output node for outputting an oscillation signal having a frequency changed in accordance with a voltage difference between the first power supply line terminal and the second power supply line;
a level converter connected to the second power supply line and a third power supply line and having an input node connected to the output node of the oscillator and an output terminal for outputting an output signal, the level converter converting an amplitude of the oscillation signal to an amplitude of the output signal corresponding to a voltage difference between the second power supply line and the third power supply line; and
a transistor connected between the first power supply line and the third power supply line and having a control electrode connected to receive a control signal so that the oscillation frequency of the oscillation signal of the oscillator is controlled by a voltage of the control signal.
In one embodiment, the second power supply line is connected to a low potential power supply voltage, and the third power supply line is connected to a high potential power supply voltage, and the transistor is an nMOS transistor having a source connected to the first power supply line and a drain connected to the third power supply line, a gate of the nMOS transistor being connected to receive the control signal.
In another embodiment, the second power supply line is connected to a high potential power supply voltage, and the third power supply line is connected to a low potential power supply voltage, and the transistor is a pMOS transistor having a source connected to the first power supply line and a drain connected to the third power supply line, a gate of the pMOS transistor being connected to receive the control signal.
In still another embodiment, the second power supply line is connected to a low potential power supply voltage, and the third power supply line is connected to a high potential power supply voltage, and the transistor is an npn transistor having a collector connected to the third power supply line and an emitter connected to the first power supply line, a base of the npn transistor being connected to receive the control signal.
In a further embodiment, the second power supply line is connected to a high potential power supply voltage, and the third power supply line is connected to a low potential power supply voltage, and the transistor is a pnp transistor having a collector connected to the third power supply line and an emitter connected to the first power supply line, a base of the pnp transistor being connected to receive the control signal.
According to still another aspect of the present invention, there is provided a voltage controlled oscillator comprising:
an oscillator connected between a first power supply line and a second power supply line and having an output node for outputting an oscillation signal having a frequency changed in accordance with a voltage difference between the first power supply line terminal and the second power supply line;
a level converter between a third power supply line and a fourth power supply line and having an input node connected to the output node of the oscillator and an output terminal for outputting an output signal, the level converter converting an amplitude of the oscillation signal to an amplitude of the output signal corresponding to a voltage difference between the third power supply line and the fourth power supply line;
a first transistor connected between the first power supply line and the third power supply line and having a control electrode connected to receive a first control signal; and
a second transistor connected between the second power supply line and the fourth power supply line and having a control electrode connected to receive a second control signal,
so that the oscillation frequency of the oscillation signal of the oscillator is controlled by a voltage of the first control signal and a voltage of the second control signal.
In one embodiment, the third power supply line is connected to a high potential power supply voltage, and the fourth power supply line is connected to a low potential power supply voltage, and wherein the first transistor is an nMOS transistor having a source connected to the first power supply line and a drain connected to the third power supply line, a gate of the nMOS transistor being connected to receive the first control signal, and the second transistor is a pMOS transistor having a source connected to the second power supply line and a drain connected to the fourth power supply line, a gate of the pMOS transistor being connected to receive the second control signal.
In another embodiment, the third power supply line is connected to a high potential power supply voltage, and the fourth power supply line is connected to a low potential power supply voltage, and wherein the first transistor is an npn transistor having a collector connected to the third power supply line and an emitter connected to the first power supply line, a base of the npn transistor being connected to receive the first control signal, and the second transistor is a pnp transistor having a collector connected to the fourth power supply line and an emitter connected to the second power supply line, a base of the pnp transistor being connected to receive the second control signal.
As explained above, the voltage controlled oscillator in accordance with the present invention realizes an excellent insensibility against a power supply voltage variation, by utilizing the nature that a potential of a source electrode of a MOS transistor is determined by a gate voltage and a drain current, independently of a voltage of a drain electrode of the MOS transistor.
In brief, the voltage controlled oscillator in accordance with the present invention is characterized in that, in an oscillator having an oscillation frequency determined by a voltage difference between a first power supply line and a second power supply line, a MOS transistor is inserted in such a manner that a source of the MOS transistor is connected to the first or second power supply line and a drain of the MOS transistor is connected to a power supply voltage which may vary. With this connection, the potential of the source of the MOS transistor is determined by a voltage applied to a gate of the MOS transistor and a drain current of the MOS transistor.
Here, the drain current itself of the MOS transistor is determined by the gate voltage of the MOS transistor and a consumption current of the oscillator, and the consumption current of the oscillator is also directly determined by the gate voltage of the MOS transistor. Therefore, the oscillation frequency of the oscillator is determined by the gate voltage of the MOS transistor. Thus, even if the voltage on the drain of the MOS transistor varies, the voltage on the source of the MOS transistor does not change, with the result that the voltage controlled oscillator in accordance with the present invention is not influenced by the power supply voltage variation.
In addition, even if a bipolar transistor is used in place of the MOS transistor, a similar advantage can be obtained.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.